1. Field of the Invention
The present invention relates to a semiconductor device including metal wiring layers such as copper (Cu) wiring layers and its manufacturing method.
2. Description of the Related Art
As semiconductor devices have been become more-finely structured, the resistance of wiring layers have been increased, and also, the parasitic capacitance therebetween has been increased. Note that the increase of resistance and the increase of parasitic capacitance in wiring layers increase time-constants thereof, which would delay the propagation of signals on the wiring layers.
In order to decrease the resistance of wiring layers, use is made of Cu rather than aluminum (Al). However, since it is difficult to subject Cu to a dry etching process, a chemical mechanical polishing (CMP) process is applied to the formation of wiring layers using Cu, which is called a damascene structure.
In a prior art method for manufacturing a single-damascene structure using Cu (see: JP-A-2000-150517), a copper layer filled in a groove of an insulating interlayer by a CMP process is completely sandwiched by a barrier metal layer and a copper diffusion barrier layer, so as to suppress the oxidation of the copper layer and diffusion of copper from the copper layer. Also, in order to suppress the electromigration of the copper layer, a Cu silicide is formed on the upper surface of the copper layer. This will be explained later in detail.
In the above-described prior art method for a single-damascene structure, however, the resistance of wiring layers is substantially increased due to the presence of Cu silicide and the oxide thereon.
On the other hand, in a prior art method for manufacturing a dual-damascene structure using Cu, a first copper layer is filled in a groove of an insulating interlayer via a barrier metal layer, and then, a copper diffusion barrier layer is formed thereon. Then, insulating interlayers are further formed on the copper diffusion barrier layer, and a via hole is formed in the insulating interlayers by a photolithography and etching process using the copper diffusion barrier layer as an etching stopper. Then, another copper layer is filled in the via hole and is connected to the first copper layer. This also will be explained later in detail.
In the above-described prior art method for a dual-damascene structure, however, the copper diffusion barrier layer may be overetched by the photolithography and etching process for the insulating interlayers, so that the first copper layer is oxidized by the post-stage dry ashing process using O2 gas plasma, which decreases the manufacturing yield and enhances the electromigration.
Note that the dual-damascene structure is mainly divided into a via first type; a middle first type; and a trench first type.
In the via first type dual damascene structure, first and second insulating interlayers are sequentially formed. Then, a via hole is formed in the first insulating interlayer, and then, a groove is formed in the second insulating interlayer. Finally, a via structure and a groove wiring layer are simultaneously formed in the via hole and the groove, respectively.
In the middle first type dual-damascene structure, a first insulating interlayer is formed, and a via hole etching mask is formed on the first insulating interlayer. Then, a second insulating interlayer is formed. Then, a groove is formed in the second insulating interlayer simultaneously with the formation of a via hole in the first insulating interlayer using the via hole as an etching mask. Finally, a via structure and a groove wiring layer are simultaneously formed in the via hole and the groove, respectively. In the middle first type dual-damascene structure, note that anti-reflective layers for suppressing reflective light from an under Cu layer cannot be used in the photolithography processes for the formation of the via hole mask and the groove.
In the trench first type dual-damascene structure, first and second insulating interlayers are sequentially formed. Then, a groove (trench) is formed in the second insulating interlayer. Then, a via hole is formed in the first insulating interlayer. Finally, a via structure and a groove wiring layer are simultaneously formed in the via hole and the groove, respectively. In the trench first type dual-damascene structure, note that an anti-reflective layer for suppressing reflective light from an under Cu layer cannot be used in the photolithography process for the formation of the via hole.
The via first type dual-damascene structure is used for finer lower wiring layers, while the middle first type and the trench first type dual-damascene structures are used for non-fine middle and upper wiring layers.